module If(
    input clk,
    input reset,
    input inst_r_valid,
    input stall_from_mem,
    input flush_if_id,

    output stall_o,
    output reg inst_r_ena
);
    assign stall_o = ~inst_r_valid;
    
    always @(posedge clk) begin
        if(reset) begin
            inst_r_ena <= 1'b0;
        end else begin
            if(stall_from_mem) begin
                inst_r_ena <= 1'b0;
            end else begin
                inst_r_ena <= 1'b1;
            end
        end
    end

endmodule
